GPU Dispatch · 2026-W37

No new NVIDIA silicon this week; Rubin CPX remains the end-of-2026 massive-context part; HBM supply crunch is the dominant ramp variable

NVDA ecosystem — weekly dispatch (2026-W37)

### Material change this week

None on NVIDIA silicon. No SKU launch, no datasheet spec revision on tracked NVIDIA products this ISO week. Catalog unchanged.

### Forward context (carry-forward, unchanged)

Rubin CPX — purpose-built GPU for massive-context inference (million-token coding, generative video):

• 128 GB GDDR7 per GPU
• Up to 30 PFLOPS NVFP4
• ~3x attention throughput vs GB300 NVL72
• Delivered in the Vera Rubin NVL144 CPX rack: 8 exaFLOPS AI compute, 100 TB fast memory, 1.7 PB/s memory bandwidth
• Stated availability: end of 2026; named early adopters include Cursor, Runway, Magic

Rubin CPX splits the inference stack — GDDR7-based context/prefill part alongside HBM-based Rubin GPUs for decode. Some secondary reporting has questioned whether the CPX part survives to volume; NVIDIA's newsroom listing still carries it. Treat the roadmap timing as vendor-stated, not independently confirmed.

### What remains the practical OEM / fleet baseline

HGX B200 — Eight Blackwell SXM GPUs, 1.4 TB aggregate memory, NVLink-5, up to 108 PFLOPS FP4 sparse at 8-GPU system level.

HGX B300 (Blackwell Ultra) — 2.1 TB total memory, 144 PFLOPS FP4 sparse at system level.

H200 — 141 GB HBM3e at 4.8 TB/s, up to 700W TDP (SXM).

GB200 / Grace Blackwell — Module/rack-scale NVL for fleets without Vera Rubin allocation.

### Supply chain — the week's real signal

Automated news this week is almost entirely memory-supply: a KB Securities note (reported 2026-09-07) puts Samsung and SK Hynix finished-DRAM inventory below 10 days. HBM4 production is described as consuming roughly 3x the wafer capacity of conventional DRAM per bit, and 2026 HBM output across all three merchant suppliers is characterised as effectively committed. New large-scale HBM cleanroom capacity is timed for 2028–2029. This is an operational constraint on accelerator ramp timelines (NVIDIA, AMD, and custom silicon alike), not a stock signal.

---

Technical research for informational purposes only. Not financial advice. No investment recommendations. Specs sourced from vendor documentation; verify before engineering or procurement decisions.

Quiet week on NVIDIA parts. The technically significant item is upstream: sub-10-day memory maker inventory means HBM allocation, not GPU design, is the gating factor for how fast Rubin and Blackwell Ultra fleets actually grow through 2027.

No new AMD or Huawei SKU this week; MI455X/Helios in the Q3 shipment window; CXMT reportedly at ~10% DRAM share

Rivals — weekly dispatch (2026-W37)

### AMD — Helios in its shipping window, no catalog change

No new Instinct launch or catalog SKU this week. AMD maintains Helios is in full production with initial shipments in the end-of-Q3 2026 window (Q3 closes Sep 30) and ramp through Q4 into 2027. AMD has publicly denied MI455X delay reports, saying H2 2026 AI GPU shipments remain on track.

Helios recap (specs unchanged):

• MI455X: 432 GB HBM4 per GPU, CDNA-next, 2nm-class process; vendor claims up to 4x MI355X peak MXFP8/MXFP4
• 72-GPU rack: ~2.9 exaFLOPS FP4, 31 TB aggregate HBM4, UALoE fabric
• Catalog note: MI455X still not in `gpu_products`; baseline remains MI355X
• Meta 6 GW multi-year AMD Instinct commitment, first gigawatt-scale shipments H2 2026

### AMD Instinct (current catalog)

MI355X — 288 GB HBM3E, 8 TB/s, CDNA4, 1400W TBP, OAM / UBB 2.0.

MI325X — 256 GB HBM3E MI300 refresh.

Software — ROCm remains the adoption variable vs CUDA.

### Huawei Ascend

Ascend 910B / 910C — China-domestic; May 2026 US guidance states worldwide use violates export controls. Huawei reportedly targeting ~600k Ascend 910C units in 2026.

Ascend 950 series (950PR / 950DT) — on Huawei's 2026 roadmap for large-scale inference (950PR cited at ~1.56 PFLOPS FP4); not independently verified, not catalogued.

### HBM / memory supply (ecosystem pressure)

• Samsung and SK Hynix finished-DRAM inventory reported below 10 days (KB Securities, 2026-09-07)
• CXMT reported at ~10% of global DRAM bit share and has started HBM3E production — a China-domestic memory path for domestic accelerators
• HBM4 pricing reported ~30% above the prior generation in Samsung negotiations
• New HBM cleanroom capacity timed for 2028–2029

Samsung's HBM page still lists HBM4E (up to 64 GB / 16H, up to 4 TB/s), HBM4, and HBM3E.

---

Technical research for informational purposes only. Not financial advice. No investment recommendations. Specs sourced from vendor documentation; verify before engineering or procurement decisions.

Rivalry narrative unchanged week-over-week. The one moving piece is memory sovereignty: CXMT at ~10% bit share plus in-house HBM3E gives China-domestic accelerators a supply path that partly routes around the export-control choke point on leading-edge HBM.